Espressif Systems /ESP32-S3 /SPI1 /USER

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Interpret as USER

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CK_OUT_EDGE)CK_OUT_EDGE 0 (FWRITE_DUAL)FWRITE_DUAL 0 (FWRITE_QUAD)FWRITE_QUAD 0 (FWRITE_DIO)FWRITE_DIO 0 (FWRITE_QIO)FWRITE_QIO 0 (USR_MISO_HIGHPART)USR_MISO_HIGHPART 0 (USR_MOSI_HIGHPART)USR_MOSI_HIGHPART 0 (USR_DUMMY_IDLE)USR_DUMMY_IDLE 0 (USR_MOSI)USR_MOSI 0 (USR_MISO)USR_MISO 0 (USR_DUMMY)USR_DUMMY 0 (USR_ADDR)USR_ADDR 0 (USR_COMMAND)USR_COMMAND

Description

SPI1 user register.

Fields

CK_OUT_EDGE

This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK.

FWRITE_DUAL

Set this bit to enable 2-bm in DOUT phase in SPI1 write operation.

FWRITE_QUAD

Set this bit to enable 4-bm in DOUT phase in SPI1 write operation.

FWRITE_DIO

Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation.

FWRITE_QIO

Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation.

USR_MISO_HIGHPART

DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable.

USR_MOSI_HIGHPART

DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable.

USR_DUMMY_IDLE

SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable.

USR_MOSI

Set this bit to enable the DOUT phase of an write-data operation.

USR_MISO

Set this bit to enable enable the DIN phase of a read-data operation.

USR_DUMMY

Set this bit to enable enable the DUMMY phase of an operation.

USR_ADDR

Set this bit to enable enable the ADDR phase of an operation.

USR_COMMAND

Set this bit to enable enable the CMD phase of an operation.

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